The invention relates to a semiconductor device comprising a semiconductor body having a surface region of a first conductivity type which borders on a surface and which is provided with a non-volatile memory in the form of a matrix of memory cells which are arranged in rows and columns, each memory cell comprising a MOS transistor having a source, a drain, a channel region situated between the source and the drain, and a gate which is situated above the channel region and which is electrically insulated from said channel region by an intermediate gate dielectric which is provided with a charge-storage region wherein data in the form of electric charge can be stored, each column comprising two zones of the opposite, i.e. the second, conductivity type, which extend throughout the length of the column and which form a common source and drain for the memory cells in the column, and the surface being covered with a number of adjacent word lines in the form of conductor tracks extending over the surface in a direction parallel to the rows, and each word line being coupled to the gates of a row of memory cells. Such devices are generally known in the literature. During writing or programming, electric charge is provided in the charge-storage region, thereby causing the threshold voltage of the transistor to be changed. The cell can be read by applying a voltage to the gate having a value between the threshold voltage of a programmed cell and the threshold voltage of a non-programmed cell, and by subsequently ascertaining whether the transistor is conducting or non-conducting at this gate voltage. The charge-storage region may be formed, for example, by a floating gate. In another embodiment, the charge-storage region is formed by the interface between an oxide layer and a nitride layer in the gate dielectric. In yet another embodiment, the charge-storage region is formed by distributing, for example, small metal particles in the gate dielectric. The matrix may be designed such that each column comprises source/drain zones which are only associated to this column. Preferably however, each zone is shared by two adjacent columns so that, with the exception of course of zones at the edges of the matrix, each zone forms a source or drain of two columns, so that a high packing density can be achieved. In the literature, such a design is commonly referred to as xe2x80x9cvirtual groundxe2x80x9d. If F is the minimum dimension which can be imaged photolithographically, then the minimum dimension of the cell according to this design in the direction of the word lines (x-direction) is 2F. In the y-direction, the cells are generally separated from each other by field oxide or an implanted region, so that the minimum dimension of a cell in the column direction (y-direction) is also 2F. This means that, in known devices, the minimum size of a memory cell is 4F2.
It is an object of the invention to provide, inter alias, a method of increasing the packing density particularly in the y-direction, so that, at a minimum photolithographic dimension F, the minimum size of a cell in the y-direction becomes equal, or at least substantially equal to F, so that the minimum size of the cell becomes only 2F2. A semiconductor device of the type described in the opening paragraph is characterized in accordance with the invention in that the channel regions of memory cells in two adjacent rows are separated from each other only by intermediate parts of the surface region of the first conductivity type, the distance between these channel regions as well as the distance between the associated word lines being small in comparison with the width of the channel region and the width of the word line, respectively.
The invention is, inter alias, based on the recognition that in a non-volatile memory maximally one word line is selected at any one time, while the other word lines are not selected, so that it is not necessary to separate adjacent channels of adjacent cells from each other by intermediate field oxide or a trench of a channel stop area. This means that, unlike conventional devices in which the space between the channels and the word lines, which has a dimension which is at least equal to the above-mentioned minimum photolithographic dimension F, is used for the isolation between adjacent cells, in a device in accordance with the invention, this space is also used for providing memory cells. By virtue thereof, the packing density in the y-direction can be practically doubled as compared to conventional memories.
Although the invention can be advantageously used in embodiments wherein each column comprises a source and drain zone belonging only to this column, a preferred embodiment is characterized in that the zones of the second conductivity type are shared by two adjacent columns of memory cells. By virtue of the fact that, in these xe2x80x9cvirtual groundxe2x80x9d embodiment, zones are shared by two adjacent columns, a higher packing density in the x-direction can be obtained. In embodiments wherein the charge-storage region in the memory cells is formed by a floating gate, the minimum size of the cell in the x-direction is 2F. A further embodiment of a device in accordance with the invention is characterized in that the charge-storage regions each comprise a collection of mutually separated trapping centers. In such an embodiment electric charge cannot only be provided in the charge-storage region throughout the channel length but also only on the source side of the channel or only the drain side of the channel. Since these different conditions can be distinguished in the reading process, it is possible to store two bits per cell in this type of memories, as described, inter alias, in the patent U.S. Pat. No. 5,426,605 by van Berkel et. al. This mode of operation enables the bit density in the x-direction to be doubled. In combination herewith, the application of the invention enables a programmable, non-volatile memory having a minimum effective cell size of only F2 to be manufactured.
In a semiconductor device in accordance with the invention, the word lines may be closely spaced so as to obtain a high packing density. A further embodiment is characterized in that the word lines include strips of doped polycrystalline silicon which are separated from each other only by thin dielectric layers covering the side walls of the strips. An embodiment in which use can be made of CCD techniques, is characterized in that the word lines are alternately formed in a first, doped polycrystalline silicon layer and a second, doped polycrystalline silicon layer which is electrically insulated from the first layer.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.